Table of Contents

1. About
2. The Assignment
3. Design
4. Final Report

About

For ESE 345: Computer Architecture, we were tasked with designing a four-stage Single Instruction Multiple Data (SIMD) multimedia unit capable of executing a custom instruction set in VHDL. The four stages and their integrated entities are the following:

1. Instruction Decode (Program Counter and an Instruction buffer that acts as an EEPROM)
2. Instruction Fetch (A Register file that fetches data based on the given addresses)
3. Execute Stage (Including a forwarding unit and an ALU)
4. Write Back (A write back unit that would control the write enable line that connects to the register file.)

The Assignment

The original assignment can be fonud in the following PDF.

Design

Following the 4 stage design laid out above, I constructed 8 entities in mostly behavioral VHDL according to the following block diagram. Each of the entities besides the register buffers has been testbenched before assembling them into an overarching structural architecture.

Final Report

The final project report can be found in the following PDF.

You can find more about the SIMD unit by visiting the Github Repo here.